PhD

Process Technology

• Ge and III-V CMOS scaling
• Post-CMOS nano
• Reliability research at IMEC
• Memories
• Power devices
• GaN Power Converters
• Nanoscale properties of new materials for emerging memory de
• Ion-solid interactions
• Probing semiconductor devices on the atomic scale
• Packaging and interconnection
• SiGe-based MEMS
• RF-MEMS
• Advanced lithography
• Simulation of wafer plating uniformity
• Superfilling of 3D via structures with alternative metals
• Diamond bit cutting for metal bonding

Packaging and interconnection

With its packaging R&D, imec wants to speed up the scaling of packaging and interconnects. This is needed to close the technology gap with semiconductor scaling, and to follow the requirements set by the ITRS roadmap. Imec also develops innovative solutions for the heterogeneous, intelligent applications of tomorrow.

The challenges include - next to further miniaturization - heat removal through the package, environmental neutral designs, cost-effective designs, chip-package co-design, and integration of passive components.

These are some of the areas that imec is working on:

• 3D integration
• Multilayer thin-film packages
• Flexible and stretchable electronics