PhD

Process Technology

• Ge and III-V CMOS scaling
• Post-CMOS nano
• Reliability research at IMEC
• Memories
• Power devices
• GaN Power Converters
• Nanoscale properties of new materials for emerging memory de
• Ion-solid interactions
• Probing semiconductor devices on the atomic scale
• Packaging and interconnection
• SiGe-based MEMS
• RF-MEMS
• Advanced lithography
• Simulation of wafer plating uniformity
• Superfilling of 3D via structures with alternative metals
• Diamond bit cutting for metal bonding

Post-CMOS nano

Within 10 to 15 years, conventional CMOS scaling will hit a brick wall induced by technological limitations. To circumvent this materials at the nanometerscale (e.g. semiconducting nanowires, carbon nano tubes, graphene, functional oxides, ...), techniques (atomic layer deposition, electrochemical processing, ...) and new concepts (e.g. tunnel FET's, MOTT transistion material devices, ...) for storage and digital processing of information will be considered to continue scaling and performance enhancement in the post-CMOS nanotechnology era. Within imec, these challenges are dealt with in multidisciplinary teams, with a clear emphasis on experimental processing as well as modelling and simulation, thus creating opportunities for chemists, physicists, material scientists and (electrical) engineers to endeavour in phd research in a vivid and stimulating environment.

Responsible scientists: Stefan De Gendt, Kristin De Meyer, Marc Heyns, Anne Verhulst, Wim Magnus