Training events and courses
CALIT
Previous Technology Aware Design Seminar:
Leuven, 23rd February 2010 - 7th CALIT Seminar on Technology-Design Interaction
Who will solve the embedded memory scaling bottleneck: technologists or designers?
Organizers: Miguel Miranda, Erik Jan Marinissen and Dirk Wouters, IMEC, Leuven, Belgium
Technology scaling has traditionally offered key advantages to embedded memory subsystems in terms of integration benefits, reduced power/energy consumption and increased performance. Memories have been the main technology drivers for aggressive process innovations and are critical components for achieving high-performance in high-end systems while being the main responsible for low-power operation on mobile appliances. However, scaling past the 45 nm technology node, process integration brings a new set of problems with negative impact on embedded memory scaling. Increased process variability limits further voltage scaling in SRAM memories while uneven scaling of material parameters limits DRAM capacitor size reduction and creates cell interference problems in Flash technologies. On the other hand, no real design breakthrough at the circuit, architecture and/or system level have proven yet to be effective enough so as to solve the traditional gap existing between the fast and cheap logic and the slow and costly embedded memory subsystem. These scaling limitations pose significant challenges to further integration capabilities on all sorts of embedded memory concepts: both volatile and non-volatile.
At this moment of time there are several emerging alternatives being considered for both volatile and non-volatile operation (i.e. Z-RAM, T-RAM, R-RAM, PCM,…). However, it is not clear whether any of those options is robust enough so as to provide a long lasting scalable solution while fitting the needs of high density, and performance and low power operation of the SoC. Solving this memory scaling bottleneck is critical for further scalability of SoC products and functionalities and it will definitely require significant innovations coming both from both technology and design communities. Moreover, from a system viewpoint, the requirements for speed, power and/or reliability are quite different depending on the SoC memory hierarchy level. In the lack of a universal memory concept, a combination of heterogeneous technologies is thus highly advisable for the implementation of the SoC memory hierarchy. Not only volatile but especially non-volatile technologies becomes attractive in this context and their design and technology choices must be tuned to meet these requirements which do not necessarily need to be the same choices as for the commodity market.
In this seminar we will evaluate pros and cons of several emerging technology alternatives and will evaluate whether they require radically new design styles. For instance, they may necessitate a fundamental shift in the way components and systems are designed that may be too disruptive to ever be absorbed by industry. Some other trade offs, such as implementation cost, quality of the solution, scalability with technology and many others will be subject of debate in this seminar as well.
Speakers, Topics, Abstracts, CV’s
Subject to change
| 09.00: | Welcome and General Intro Herman Maes. VP, IMEC, Belgium |
| 09.10: | Scaling Trends for Established and Emerging Memory Technologies Dr. Betty Prince, Memory Strategies International, TX, USA Abstract & CV |
| 10.00: | Scaling trends and development avenues for DRAM Dr. Robert Patti, Tezzaron Semiconductor, IL, USA Abstract & CV |
| 10.50: | Coffee Break |
| 11.10: | Scaling Challenges for Embedded SRAM Dr. Rob Aitken , ARM ltd., US Abstract & CV |
| 12.00 | Lunch |
| 13.20: | Phase Change Memory as Storage Class Memory - Opportunities and Challenges Dr. Chung H. Lam, IBM T.J.Watson Research Center, NY, USA Abstract & CV |
| 14.10: | Z-RAM floating body memory for high density embedded and standalone RAM memories Dr. Pierre Fazan, Innovative Silicon, Switzerland Abstract & CV |
| 15.00 | Coffee break |
| 15.20 | Variability Resilient Yet Low Power SRAM design Prof. Wim Dehaene, Katholieke Univ. Leuven, Belgium Abstract & CV |
| 16.10 | Panel: Design vs Technology: Who will Solve the embedded memory scaling bottleneck? Panelists: Rob Aitken (ARM), Wim Dehaene (KULeuven), Pierre Fazan (Innovative Silicon), Chung Lam (IBM), Robert Patti (Terrazon Semiconductor), Betty Prince (Memory Strategies, Intl.), Jan Van Houdt (IMEC) Moderator: Dirk Wouters (IMEC) |
| 17.30: | End of program |
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