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Robert PATTI || 23 February || CALIT Seminar on Technology-Design Interaction

Scaling trends and development avenues for DRAM

Robert Patti, Tezzaron Semiconductor Corp., IL, USA

Abstract

Memory speed, in both latency and bandwidth, is critical to system performance. The last 3 decades have seen only small latency improvements and modest gains in bandwidth. Today, memory speed enhancements drive system performance as never before. 3D integration opens the door to upgraded memories and better memory system performance while maintaining the density and cost advantages that the industry relies on. A key opportunity in 3D is building memory in two separately optimized processes – one for memory cells, the other for sensing, I/O, and other logic functions. This process separation augments the physical advantages of 3D architecture to improve performance, power, and reliability. During this session we will look at how 3D memory architecture can improve both DRAM memories and entire systems, and how these improvements will apply to emerging memory technologies. Topics touched on: 3D DRAM architecture, line caching, self test and self repair, smart memories, hybrid memory

CV

Bob Patti attended Rose-Hulman Institute of Technology, earning bachelor of Science degrees in both physics and electrical engineering. He founded an R&D company specializing in high-performance systems and ASICs and participated in the design of over 100 chips in the course of 12 years. Tezzaron Semiconductor grew from that company to become a leading force in 3D-IC technology, building its first working 3D-ICs in 2004. Today Bob is the CTO of Tezzaron, using wafer-level stacking processes to create ultra high-density 3D memory products and other semiconductor sub-components. He received the SEMI Award for North America in 2009, served as Vice-Chairman of JEDEC's DDRIII / Future Memories Task Group, and holds 14 US patents, numerous foreign patents, and many more pending patent applications in deep sub-micron semiconductor chip technologies. split die memory, multi-terabit I/O.