Training events and courses
CALIT
Leuven, October 20th and 21st 2011 - 1st International Workshop on Resistive RAM
Imec and Stanford NMTRI* are jointly organizing the 1st International Workshop on Resistive RAM, addressing all aspects of RRAM (including oxide-based RRAM, CBRAM, selector, and array considerations). The workshop will be held at Imec, Leuven, Belgium, on October 20th and 21st (Thursday and Friday), 2011, and will be supported by imec’s Center of Advanced Learning in Information Technologies (CALIT).
Resistive memories are seen today as one of the most promising emerging candidates to become a key memory technology of the future, with many potential applications, ranging from replacement of current mass production commodity memories to embedded applications and even creating novel market segments.
The intention is for this workshop to serve as a forum gathering key scientists and technologists working on RRAM, including academia as well as industry, to discuss both the fundamental mechanisms controlling the operation, scalability and reliability as well as technological potential and challenges of these exciting memories.
The workshop will consist of invited talks and panel discussions, as well as a poster session. Participation is by invitation.
*Stanford NMTRI (Nonvolatile Memory Technology Research Initiative) is an industrial affiliate program at Stanford. URL: http://nmtri.stanford.edu/
Speakers, Topics, Abstracts, CV’s
Thursday, October 20th, 2011
| 09.00: | Welcome and Opening Remarks J. A. Kittl/L. Van den Hove (Imec, Belgium) |
| 09.15: | Keynote: Resistive Switching Memory (RRAM) – Modeling and Scaling Studies H. -S. P. Wong (Stanford, USA) |
| 09.55: | Keynote: Microscopic Processes in Redox-Based Resistive Switching R. Waser (Jülich-Aachen Research Alliance-FIT, Germany) |
| 10.35: | Coffee Break |
| 10.55: | Keynote: Collective motion of nano-filaments in Pt/n-type TiO2/p-type NiO/Pt stacked resistance switching memory C. S. Hwang (Seoul National University, Korea) |
| 11.35: | Resistive Random Access Memory: Technology and Applications F. Chen (ITRI, Taiwan) |
| 12.00 | Lunch |
| 13.30: | Progress and Challenges on Resistive RAM J. A. Kittl (Imec, Belgium) |
| 13.55: | Modeling filament conduction R. Degraeve (Imec, Belgium) |
| 14.20 | Coffee break |
| 14.40 | Mechanisms and modeling of filamentary switching in bipolar metal-oxide RRAM D. Ielmini (Politecnico di Milano, Italy) |
| 15.05 | Oxide-Based RRAM-Unified Physical Mechanism and Implementation for Cell Design Optimization J. Kang (Peking University, China) |
| 15.30 | Physical modeling of HfO2 RRAM device operations L. Larcher (Università di Modena e Reggio Emilia, Italy) |
| 16.00: | Poster Session/Reception |
| 18.30: | Panel Discussion: “What is the switching mechanism of metal oxide RRAM?” Panelists: H. Akinaga (AIST, Japan), R. Waser (JARA, Germany), C. S. Hwang (Seoul National University, Korea), D. Ielmini (Politecnico di Milano, Italy), Y. Nishi (Stanford, USA), F. Chen (ITRI, Taiwan), L. Larcher (Università di Modena, Italy) |
Friday, October 21st, 2011
| 09.00: | Opportunities and Risks of the Resistive Memory in the Future Memory Market I. G. Baek (Samsung, Korea) |
| 09.25: | Emerging Memory Opportunities, Promise and Challenges G. Sandhu (Micron, USA) |
| 9.50: | Hf-based RRAM: towards 10 nm B. Govoreanu (Imec, Belgium) |
| 10.15: | Coffee Break |
| 10.35: | Keynote: Ionic memory M. Kozicki (Adesto, USA) |
| 11.00: | Triode atom-switch T. Sakamoto (LEAP(NEC), Japan) |
| 11.25: | Physics of Ag/GeSx/W CBRAM cells J. R. Jameson (Adesto, USA) |
| 12.00 | Lunch |
| 13.30: | Tungsten-oxide ReRAM and Cu-based Multiple-layer CBRAM E. Lee (Macronix,Taiwan) |
| 13.55: | Cu-Te based CBRAM L. Goux (Imec, Belgium) |
| 14.20: | Kinetic Monte-Carlo Modeling of Electrochemical Metallization RRAMs V. Subramanian (U.C. Berkeley, USA) |
| 14.45: | RRAM memories for advanced CMOS integration J.Buckley (CEA-LETI-MINATEC, France) |
| 15.10: | ReRAM and CBRAM devices using AlOx and Ge-based materials S. Maikap (Chang Gung University, China) |
| 15.35 | Coffee break |
| 15.55 | SSelector considerations for RRA G. Spadini (Intel, USA) |
| 16.20 | Selection devices for Resistive Switching Memories (RRAM) A. Chen (Global Foundries, USA) |
| 16.45 | Access Device Options for 3D Crosspoint RRAM Arrays K. Gopalakrishnan (IBM, USA) |
| 16.45 | Coffee Break |
| 17.30: | Panel Discussion: “Which emerging memory for what applications?” Panelists: G. Sandhu (Micron, USA), G. Spadini (Intel, USA), T. Sakamoto (NEC, Japan), I. G. Baek (Samsung, Korea),R. Srivastava (Sandisk), R. Liu (Macronix, Taiwan), C. Lam (IBM, USA), N. Derhacobian (Adesto, USA) |
Organizing Committee:
| Dr. J. A. Kittl | Prof. H.-S. P. Wong | Prof. Y. Nishi | Prof. H. Maes |
| Chief Scientist, Imec | Stanford University | Stanford University | Sr. VP Imec, Coordinator CALIT |
kittlj@imec.be | hspwong@stanford.edu | nishiy@stanford.edu | maesh@imec.be |
We recommend following hotels in Leuven:
- Novotel Leuven Centre (http://bit.ly/nmao1p): imec rate € 135 single room including breakfast
Use the inscription form to make your reservation before September 12th 2011. - Hotel Binnenhof (http://www.hotelbinnenhof.be/): imec rate € 116 single room including breakfast
Send an e-mail to info@hotelbinnenhof.be and mention the following code “G70168”. Make your reservation before September 19th 2011.These hotels are located near the railway station of Leuven. You can reach imec by taxi or by bus. More information on how to reach imec.
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