IMEC, Europe's leading independent nanoelectronics and nanotechnology research institute, extends its 193nm immersion lithography research program with double-patterning techniques to meet the stringent scaling roadmaps, especially of Flash. The program now runs hyper-NA immersion, double-patterning immersion and EUV in parallel.

Extreme UV will be needed to accommodate the pitch requirements for sub-32nm CMOS, but it still has a long way to go before it can be inserted into manufacturing. As such, 193nm immersion lithography needs to be extended down to 32nm CMOS and will consequently be pushed to its limits, including hyper-NA immersion. To meet the stringent scaling roadmaps, especially of Flash, extensive use of double-patterning techniques may also be required. IMEC now runs research programs on hyper-NA immersion, double-patterning immersion and EUV in parallel to deal with the challenges for the (sub)-32nm node.

Within the hyper-NA research program, IMEC focuses on alternative mask stacks, high-index liquids and resists, XT:1700i lens and illumination characterization and immersion baseline including resist, defectivity and scanner. IMEC will leverage on the numerous breakthrough results achieved over the past year in its 193nm immersion program: reduction of patterned defectivity, improvement of CD uniformity and overlay performance.

IMEC’s double patterning research will be strongly linked with its device programs on advanced CMOS for logic and also in its advanced-memory program. Double-patterning research topics include layout-split methodology and exploration of alternative patterning steps to improve double-patterning cost of ownership. Existing research in the Flash program are the study of new cell concepts (nitride concept), implementation of high-k materials, reliability and characterization. Several advanced logic and Flash cells will be used as demonstrators in IMEC’s program on (sub-)32nm lithography.

Research within IMEC’s EUV program includes resists and reticles development and assessment of the EUV alpha demo tool.

"With the three lithography programs running in parallel, we offer a unique platform to our partners to meet the stringent lithography challenges for the (sub)-32nm node. Leveraging on our expertise and strong partnerships, we are convinced that our programs, with ASML’s state-of-the-art tools as cornerstone, will enable our partners to keep up with the ITRS roadmap;" said Luc Van den hove, Vice President Silicon Process and Device Technology at IMEC.

For more information:

Katrien Marent
Corporate Communication Manager
IMEC, Kapeldreef 75
B- 3001 Leuven, Belgium
Tel +32 16 28 18 80 Fax +32 16 28 16 37
Email: Katrien.Marent@imec.be