At today’s International Solid State Circuit Conference, IMEC presents an ultra-low power (0.7mW) high-speed (50Msamples/s) analog to digital converter (ADC) with a figure of merit 2.5 times better compared to the best ADC ever reported. The ADC is especially suited for nomadic applications and is scalable in clock rate and towards the 45nm CMOS technology node and below.

ADC’s with 8 to 10 bits accuracy operating at several tens of Msamples/s have up to now been the territory of pipeline architectures resulting in large power consumption. Nomadic applications such as software-defined radio analog front-ends however require high-accuracy high-speed ADC’s at very low power consumption.

IMEC realized an ADC for nomadic applications with record performance by using a unique concept that combines a conventional successive approximation (SAR) architecture with passive charge sharing. The architecture works completely in the charge domain. The fundamental power limits of the original SAR architecture are overcome by doing all the charge redistribution passively. The only active elements in the ADC are the comparator and digital controller enabling ultra-low power consumption. Since the comparator doesn’t consume any power during inactive mode, the power consumption of the ADC scales linearly with the sampling frequency.

The chip was implemented in a 90nm digital CMOS technology and has a total area of 1.2x1.1mm2 from which 400x200µm2 is used by the ADC core. Measurements on silicon show a power consumption of only 0.7mW at a sampling rate of 50Msamples/s. The measured INL (integral non-linearity) and DNL (differential non-linearity) are below 0.6LSB (least significant bit). The ADC has a figure of merit of 65fJ per conversion step which is 2.5 times better compared to the best ADC ever reported and 5 times better compared to state-of-the-art ADC’s designed for nomadic applications. As none of the ADC building blocks consumes any static power, the figure of merit is maintained down to very low conversion rate.

The fully digital implementation of the ADC requires only MOS switches and metal-oxide-metal capacitors, making the ADC scalable towards the 45nm node and beyond.

For more information:

Katrien Marent
Corporate Communication Manager
IMEC, Kapeldreef 75
B- 3001 Leuven, Belgium
Tel +32 16 28 18 80 Fax +32 16 28 16 37
Email: Katrien.Marent@imec.be