A new ultra-low power (0.7 mW), high-speed (50MSamples/s) analog to digital converter, presented by IMEC at this year's ISSCC conference, achieves a figure of merit of 65fJ per conversion step. This is 2.5 times better than the best ADC of this kind ever reported in research papers and an order of magnitude better than the best commercially available ADC IP blocks in 90nm CMOS. The novel IMEC SAR ADC design is especially suited for nomadic applications in the IT realm. Its power scales linearly with the clock rate over a very wide range which makes it very well suited for software-defined radio applications. It is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45nm CMOS node and below. The design is available as 'white box IP' for transfer to the industry.

The novel SAR ADC design is related to the world’s first true software-defined radio front-end IC also presented by IMEC at ISSCC 2007. This front-end chip is widely programmable for all present and future standards between 174MHz and 6GHz. As low power consumption is of utmost importance for next-generation handheld and battery-powered devices, the new SAR ADC is a perfect match for future software-defined radio applications.

Instead of the active charge redistribution in the capacitor arrays of a conventional successive approximation (SAR) architecture, the low-power architecture of the new SAR ADC uses a passive charge-sharing concept to sample the input signal and to perform the successive-approximation cycling. As a consequence, the SAR operation is no longer based on voltage comparisons. It operates completely in the charge domain, which yields the record performance of the new IMEC design.

This way, the fundamental power limits of the original SAR architecture are overcome - by doing all the charge redistribution passively. The only active elements in the IMEC SAR ADC are the comparator and digital controller, so enabling ultra-low power consumption. Since the comparator doesn’t consume any power during inactive mode, the power consumption of the ADC scales linearly with the sampling frequency. This helps maintaining the record figure of merit down to very low conversion rates.

The fully digital implementation of the ADC requires only MOS switches and metal-oxide-metal capacitors, making the ADC scalable towards the 45nm node and beyond. The new IMEC SAR ADC outperforms all state-of-the art commercial ADCs by a factor of 10. It is 3.7 times better than ADCs in the same process generation (90 nm) and it is by a factor 2.5 better than any other high-speed research ADC.

More information: http://www.imec.be/ovinter/static_business/market.shtml

Specifications:

- Technology:  90nm digital CMOS

- Resolution:  9 bit (scalable)

- Sample rate: 50Msamples/s

- Power consumption: 0.7mW

- Figure of Merit:  65fJ/conversion step

- INL and DNL: below 0.6 LSB

- ADC core size: 400x200µm2

For more information:

Stephane Donnay
Technical Business Director IMEC
IMEC, Kapeldreef 75
B- 3001 Leuven, Belgium
Tel +32 16 28 12 23 
Email: Stephane.Donnay@imec.be