The paper ‘Impact of thinning and through silicon via proximity on high-k/metal gate first CMOS performance’ has been selected as one of the VLSI 2010 Symposia highlight papers (http://www.vlsisymposium.org).

This paper reports for the first time the impact of wafer thinning and of the proximity of through silicon via on active devices, back-end structures, ring oscillators and mixed signal circuit for a high-k/metal gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Authors of the paper are A. Mercha, A. Redolfi, M. Stucchi, N. Minas, J. Van Olmen, S. Thangaraju, D. Velenis, S. Domae¹, Y. Yang⁴, G. Katti⁴, R. Labie, C. Okoro⁴, M. Zhao, P. Asimakopoulos, I. De Wolf⁵, T. Chiarella, T. Schram, E. Rohr, A. Van Ammel, A. Jourdain, W. Ruythooren, S. Armini. A. Radisic, H. Philipsen, N. Heylen, M. Kostermans, P. Jaenen, E. Sleeckx, D. Sabuncuoglu Tezcan, I. Debusschere, P. Soussan, D. Perry², G. Van der Plas, J.H. Cho³, P. Marchal, Y. Travaly, E. Beyne, S. Biesemans, B. Swinnen (imec, assignee at imec from ¹Panasonic, ²Qualcomm, ³Samsung, ⁴imec and K.U.Leuven).