Scaling-driven nanoelectronics

3D integration: design and architecture of 3D ICs

To keep on reducing the cost of ICs per function, one possibility is to move to 3-dimensional stacking of chips. 3D chip stacking allows extending the number of functions on a chip well beyond the near-term capacity of traditional scaling. But this presumes an efficient use of the 3D real-estate, and is challenging both from the perspective of design and technology.

The technology needed for 3D stacking consists of three main processes. Imec studies new technologies and materials for each of these areas.

  1. The through-Si via process
  2. Processes for bonding and thinning wafers on carriers, allowing for backside processing on thinned wafers
  3. The actual chip stacking and stack packaging

Another key topic of our 3D research program is the design of 3D systems. 3D system design exploration steers the direction of the process development, and new technology is an enabler for improved system design. Imec has developed a pathfinding flow to study the system-level trade-offs at an early phase of the system design.

Imec participates in road mapping and standardization activities where appropriate.

See here for more information on the 3D integration program.