Scaling-driven nanoelectronics

3D integration: design and architecture of 3D ICs

• 3D systems-in-a-package
• 3D wafer-level packaging
• 3D stacked IC and 3D IC
• 3D design
• Packaging reliability

Imec has expanded its 3D research program with the exploration of new design methodologies. The aim is to understand and exploit novel 3D technologies and to limit the 3D integration cost.

Invent - To filter the mainstream 3D technologies of tomorrow from the many technology and design options of today, imec has started a track of holistic pathfinding. The aim is to find solutions for various critical design issues. It will result in better methods to partition and stack IC units, and to use the available 3D real-estate and interconnections.

Achieve - In 2009, Javelin Design Automation announced a revolutionary solution for the rapid design exploration and optimization of three dimensional stacked ICs (3D SIC).  Developed in close collaboration with imec and Qualcomm, a partner in imec’s 3D integration program, 3D PathFinding supports virtual chip design for co-optimization of system design and 3D interconnect-packaging technology.