Scaling-driven nanoelectronics
3D integration: design and architecture of 3D ICs
In 3D WLP, the structures for the 3D interconnects (the vias) are made in the wafers during the chip fabrication process. The actual connection between chips is made during the chip packaging. The vias ensure a direct connection between the chips, not going via the chip package. 3D-WLP is a 3D integration technology based on wafer-level-packaging infrastructure and technology, such as redistribution and flip-chip bumping. The 3D-WLP vias correspond to interconnects at the bond-pad level.
Invent - Imec studies three 3D WLP approaches, aiming at a cost-effective and reliable solution: post-passivation 3D Si vias, die-to-wafer or wafer-to-wafer micro-bump bonding, and ultrathin-chip stacking (UTCS), using chips that are typically 15μm thick.