Scaling-driven nanoelectronics

Memory technology

To scale Flash memory to the (sub-)22nm nodes, imec works on:

  • New materials: high-k materials for the interpoly dielectric
  • New designs: engineered tunnel barriers
  • New concepts: charge trapping devices, nitride-trapping devices (TANOS)

To scale DRAM memory, imec investigates:

  • New materials: new capacitor materials meeting aggressive specifications for equivalent oxide thickness (EOT) and leakage.
  • Optimized transistor designs with advanced junction technology, strain engineering, and high-k/metal gates.